Date: March 25, 2025
Venue: 5B+5C, Shanghai International Convention Center


Topic: Advanced Package and 3DIC (Chiplets and HBM)
   

Time: 15:30-16:15

Speaker: Dr. Guorong Li, Vice President, Beijing NAURA Technology Group Co., Ltd.


Abstract:

Currently, as Moore's Law progresses towards its limit, advanced packaging technologies such as TSV (Through Silicon Via) as a representative of 2.5D & 3D packaging have become an important way for chip higher integration. Etching process is the key and difficult point in the entire advanced packaging technology. The main difficulties are the morphology control of high aspect ratio (AR greater than 30:1) etching, such as sidewall roughness, lateral side etch control of the stopper layer, and edge inclination control. The other difficult point is the etching technology for the backside leakage of TSV after Cu filling. It involves the challenges of particle pollution control, cost control, and mass production stability. After years of technological exploration and development, NAURA has already achieved stable mass production of TSV process, backside Cu leakage process, and other multi-step etching processes for several customers.

Biography:

Dr. Li Guorong graduated from the Electronics and Information major at Peking University. He is currently the Vice president of Etch I BU and in charge of the 12-inch Etching Product Line at NAURA Co., Ltd., with over ten years of experience in the semiconductor etching equipment field. He is an expert in developing front-end and packaging process and equipment solutions, and has rich experience in the development and mass production of ICP and CCP etching equipment.
   


Time: 16:15-17:00

Speaker: Dr. Xia Jiang, Chief Scientist, JCET Semiconductor Integration (Shaoxing) Co., Ltd., China


Abstract:

In the post-Moore era, advanced packaging technologies represented by 2.5D/3D are gradually becoming a new breakthrough in the semiconductor industry. The report details the history of the development of advanced packaging, introduces and interprets representative advanced packaging technologies and processes of the present day, especially the high-bandwidth memory (HBM) die integration packaging structure based on 3D stacking. It also elaborates on the applications and development trends of HBM based on 3D packaging.

Biography:

Xia Jiang, Ph.D., Chief Scientist at JCET Semiconductor Integration (Shaoxing) Co., Ltd. He has been working on the R&D and manufacturing of 2.5D/3D wafer-level fan-out advanced packaging technologies. Focusing on high-performance chip integration such as HBM, GPU, CPU, APU, he has lead multiple development projects on ultra-high-speed, low-latency fused interconnect chiplet packaging. He is the author and co-author of multiple research papers, book, and invention patents.