Symposium Chair: Prof. Cheng Zhuo, Zhejiang University, China
| ** | to designate keynote talk - 30 min | |||
| * | to designate invite talk - 25 min | |||
| to designate regular talk - 15 min |
Monday, March 24, 2025 Shanghai International Convention Center
Session I: Advances in AI vs. Semiconductor Technologies
Meeting Room:
Session Chair: Cheng Zhuo
| **13:00-13:30 | Machine Learning for the Design of MEMS Devices |
| Michael Kraft, KU Leuven | |
| **13:30-14:00 | Large scale silicon photonics and system |
| Xingjun Wang, Peking University | |
| *14:00-14:25 | FabGPT for Smart IC Manufacturing: Overcoming Challenges in Data, Multimodality, and Deployment |
| Qi Sun, Zhejiang University | |
| *14:25-14:50 | Innovative Deep Learning Algorithm for Improving Defect Inspection Performance of E-Beam Inspection Equipment |
| Chunying Han, Dongfang Jingyuan Electron Co., Ltd. | |
| *14:50-15:15 | Pioneering Decision Systems in Semiconductor Manufacturing: Harnessing Mixture- of - Agents Networks with Multi-Modal LLMs to Integrate Engineering Expertise |
| Andrew Guan, Shenzhen FutureFab.AI Software Inc. | |
| 15:15-15:45 | Coffee Break |
| 15:45-17:55 | Poster Session |
Tuesday, March 25, 2025 Shanghai International Convention Center
Meeting Room:
Session II: Industrial Perspectives on Advanced Semiconductor Design and Manufacturing
Session Chair: Jinfeng Kang
| 08:30-08:45 | Optimization Directions and Solutions for AMHS in Large-Scale Semiconductor Fabs |
| Ming Liu, Huaxin (Jiaxing) Intelligent Manufacturing Co., Ltd. | |
| 08:45-09:00 | Zero-defect Solutions for Automotive Semiconductor Devices Manufacturing |
| Caigan (Chris) Chen, Lam Research | |
| **09:00-09:30 | The Multi-physics Simulation and Optimization for AI Hardware Systems |
| Wenliang Dai, Xpeedic | |
| 09:30-09:55 | Accelerating Power Signoff for 3DIC Design |
| Zhuo Xie, Hangzhou Xinspector Electronic Technology Co., Ltd. | |
| 09:55-10:10 | Coffee Break |
Session III: Innovations for Next Generation Semiconductor Scaling
Session Chair: Ye Lu
| *10:10-10:35 | Reliability-Aware DTCO: A Key Strategy for Post-Moore Semiconductor Scaling |
| Zhigang Ji, Shanghai Jiao Tong University | |
| *10:35-11:00 | Computational Lithography Empowered by Artificial Intelligence and Large Models |
| Hao Geng, Shanghai Tech University | |
| 11:00-11:15 | A Novel Two-stage Method for Deploying AI Models on RRAM-based Compute-in-memory System |
| Ruihua Yu, Tsinghua University | |
| 11:15-11:30 | Machine Learning to Model and Predict Layout Dependent Effects on 55nm Low Power Platform |
| Gang Wang, Hangzhou GHS Semiconductor Corporation | |
| 11:30-13:30 | Lunch Break |
Session IV: Advanced Device Design and Post-Moore Computing
Session Chair: Hao Geng
| *13:30-13:55 | Thin film transistor for temporal self-adaptive reservoir computing with closed-loop architecture |
| Peng Huang, Peking University | |
| *13:55-14:20 | AI-Assisted Techniques for Taming Device Variations in Non-Volatile Memory-Based Systems |
| Zheyu Yan, Zhejiang University | |
| 14:20-14:35 | Inverse Design for LDMOS Device Based on Machine Learning |
| Wei Si, Nanjing University | |
| 14:35-14:50 | Enhanced On-State Current and Reduced Contact Resistance in TiO₂ Channel HfLaO FeFETs via Post-Metallization Annealing |
| Dijiang Sun, Peking University | |
| 14:50-15:05 | Dual-gate 2T0C Gain Cell for Multi-bit Input Vector-matrix Multiplication In-Memory Computing |
| Jianglin Luo, Beijing Super-String Memory Academy of Technology | |
| 15:05-15:20 | Coffee Break |
Session V: Cutting-Edge Approaches to Circuit Design, Process Control, and Testing
Session Chair: Zheyu Yan
| *15:20-15:45 | TBD |
| Fan Yang, Fudan University | |
| 15:45-16:00 | A High-Resolution, ns-Range Linear Time-to-Digital Converter circuit Design for Timing Parameter Measurement |
| Yanhui Zhao, Zhejiang University | |
| 16:00-16:15 | Machine Learning-Enhanced Equivalent Circuit Modeling for Advanced Packaging Components |
| Tao Xu, Zhejiang University | |
| 16:15-16:30 | Analysis and Improvement of High Temperature LU Problem in Advanced Process RF Chip |
| Yanwei Tian, Sanechips Technology Co.,Ltd. | |
| 16:30-16:45 | A Diffusion-Based Approach to Wafer Defect Image Generation in Semiconductor Manufacturing |
| Xiaotian Qiu, Zhejiang University | |
| 16:45-17:00 | Interpretable Virtual Metrology-Driven Adaptive dEWMA Control for Nonlinear Semiconductor Process Optimization |
| Shunyuan Lou, Zhejiang University | |
| 17:00-17:15 | V93000 Solution Adapted to The Evolution of DFT Technology |
| Kevin Yan, Advantest | |
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Poster Session: |
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| Enhancing Predictive Performance and Efficiency in CMOS with Optimized CNN Hyperparameters | |
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Yuxuan Zhu, Fudan University |
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Abnormal EPI Pattern Failure Mode Analysis with Virtual Farbrication |
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Chohan Lee, Lam Research |
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Overcoming Small Sample Size Challenges in Lithography Process Window Analysis through DCGAN-Based Augmentation |
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Zeyang Chen, Zhejiang University |
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RNN-Based Proxy Modeling for TCAD Simulation of Trench MOSFET Manufacturing Processes |
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Mingqiang Geng, Zhejiang University |
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Automated Layout Design for High Frequency Integrated Circuits Based on Reinforcement Learning |
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Yifan Xu, Fudan University |
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Classification and Recognition Methods for Wafer Defect Detection |
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Ming Guo, Shanghai Huali Integrated Circuit Corporation |
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An Efficient Automatic Design Method for LDMOS Devices Based on Particle Swarm Optimization |
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Chenggang Xu, Zhejiang University |
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Investigation of NOR flash Floating Gate (FG) Residue defect improve |
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Yajun Duan, Shanghai Huali microelectronics Corporation |
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A Model using Plasma Enhanced Vapor Chemical Deposition of Silicon Nitride side Walls |
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Zhihao Li, Zhejiang University |
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A Novel Inversion Approach for Predicting Critical Etch Dimensions Based on Electrical Parameters |
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Nini ji, Zhejiang University |
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Automatic Defect Fatality Analysis and Killer-defect Identification System Based on Deep Learning |
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Ruyue Jing, Zhejiang University |
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Predicting Film Thickness and Properties in Cesl Process Based on Cgan |
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Jinxu Liu, Zhejiang University |
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Successful Matching of VIISta MEHD2 with Batch Implanter on Legacy Device |
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Huang Zeng, Applied Materials (China), Inc. |
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A Study on Correlation between WAT and CP Yields Based on Deep Learning Methods |
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Jingji Mu, Zhejiang University |
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A Low-power multi-core SNN Co-processor with Subminiature Scalable Near-memory MAC Module |
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Chenhao Tang, Zhejiang University |
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A High Efficiency and Reconfigurable Neuromorphic Engine with Parallel-pipeline Pooling Scheme |
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Yue Cheng, Zhejiang University |
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Real-Time Scheduling for Multi-Cluster Tools with Multi-type Wafers by Deep Reinforcement Learning |
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Dewei Zhu, Zhejiang University |
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A Super-Resolution Method for Non-Uniform Mesh Data Based on Deep Neural Networks |
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Qinxin Wu, Zhejiang University |
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Low-k Anneal Process Development in Logic Devices |
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Jian Zhong, Applied Materials (China), Inc. |
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Research on WIP Dispatch Rules Base on Dynamic Standard Whole Process Cycle Time |
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Rongyao Shang, Peking University |