| ** | to designate keynote talk - 30 min | |||
| * | to designate invite talk - 25 min | |||
| to designate regular talk - 15 min |
Monday, June 26, 2023 Shanghai International Convention Center
Meeting Room: 3E
Session I: Perspective and Frontier of EDA
Session Chair: Weikang Qian, Shanghai Jiao Tong University
| 13:30-13:35 | Opening Remarks |
| Weikang Qian, Shanghai Jiao Tong University | |
| **13:35-14:05 | Design Tools for Adiabatic Quantum-Flux-Parametron Logic: Toward Extremely Energy-Efficient Computing |
| Tsung-Yi Ho, Chinese University of Hong Kong | |
| *14:05-14:30 | Logic synthesis and some of its challenges |
| Yong Xiao, Giga Design Automation Co., Ltd. | |
| *14:30-14:55 | Essential Steps to Analyze Effective Resistance of ESD Paths-PG Routing Network Pruning and Resistance Contribution by Layer |
| Frank Feng, Synopsys Inc. | |
| 14:55-15:10 | Logic Circuit Simulation based on Semi-Tensor Product |
| Zhufei Chu, Ningbo University | |
| 15:10-15:25 | CirSAT: An Efficient Circuit-based SAT Solver via Fanout-driven Decision Heuristic |
| Zhufei Chu, Ningbo University | |
| 15:25-15:40 | RLCkt: An Analog Circuit Automatic Sizing Sage Based on Reinforcement Learning |
| Wangge Zuo, Fudan University | |
| 15:40-15:55 | Coffee Break |
Session II: In-Memory Computing
Session Chair: Xinfei Guo, Shanghai Jiao Tong University
| *15:55-16:20 | Compute-in-ROM: How to Achieve Both High Density and High Flexibility? |
| Xueqing Li, Tsinghua University | |
| *16:20-16:45 | Break the Memory Wall: Cross-Layer Co-Design for Energy Efficient Machine Learning SoCs |
| Chixiao Chen, Fudan University | |
| *16:45-17:10 | STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell for AI Inference |
| Hao Cai, Southeast University | |
| *17:10-17:35 | CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation |
| Li Zhang, Technical University of Darmstadt | |
Tuesday, June 27, 2023 Shanghai International Convention Center
Meeting Room: 3E
Session III: Design of AI Accelerators
Session Chair: An Zhou, Shanghai Jiao Tong University
| **8:30-9:00 | Co-Design of Binarized Deep Learning |
| Zhiru Zhang, Cornell University | |
| *9:00-9:25 | Efficient Deep Learning Accelerators Based on Multimodal Model Compression |
| Jun Lin, Nanjing University | |
| *9:25-9:50 | Efficient Multi-Modal AI Acceleration |
| Meng Li, Peking University | |
| 9:50-10:05 | Efficient partitioning and communication scheme based distributed edge computing to accelerate deep neural network |
| Xudong Lu, Zhejiang University | |
| 10:05-10:20 | Post-training Quantization or Quantization-aware Training? That is the Question |
| Xiaotian Zhao, Shanghai Jiao Tong University | |
| 10:20-10:35 | Coffee Break |
Session IV: Hardware Acceleration and Scheduling
Session Chair: Meng Li, Peking University
| **10:35-11:05 | Ultra-Fast FPGA Acceleration of Graph Cut Algorithms |
| Yajun Ha, ShanghaiTech University | |
| *11:05-11:30 | Integrated System Design for Neural Radiance Field Rendering |
| Xin Lou, ShanghaiTechUniversity | |
| *11:30-11:55 | Real-time Scheduling of Hard Deadline Tasks on a Heterogeneous Architecture |
| An Zou, Shanghai Jiao Tong University | |
| 11:55-13:30 | Lunch Break |
Session V: AI for EDA
Session Chair: Xunzhao Yin, Zhejiang University
| **13:30-14:00 | Agile Sign-Off for Sub-Nanometer VLSI Designs in the Post-Moore Era |
| Cheng Zhuo, Zhejiang University | |
| *14:00-14:25 | AI and GPU accelerated large-scale transistor-level nonlinear circuit simulation |
| Zhou Jin, China University of Petroleum | |
| *14:25-14:50 | Learning Based Electromigration Induced Stress Evolution Analysis for Multi-segment Interconnect Wires |
| Haibao Chen, Shanghai Jiao Tong University | |
| 14:50-15:05 | Learning-Based Performance and Power Model for Processor Microsecond DVFS |
| Yingtao Shen, Shanghai Jiao Tong University | |
| 15:05-15:20 | Fast NoC Router Latency Estimation Using Machine Learning |
| Yang Li, ShanghaiTech University | |
| 15:20-15:35 | Artificial Neural Network Compact Modeling Methodology for Complementary Field Effect Transistor (CFET) |
| Owen Tao, Fudan University | |
| 15:35-15:50 | Coffee Break |
Session VI: Spiking Neural Network and Analog Design
Session Chair: Zhou Jin, China University of Petroleum
| 15:50-16:05 | A Hybrid Training Framework for Speeding up the Inference Process of Spiking Neural Networks |
| Ziwen Li, ShanghaiTech University | |
| 16:05-16:20 | An 18-Bit 2MSPS SAR ADC with Double Passive Noise-Shaping Calibration |
| Xiaowei Zhang, Zhejiang University | |
| 16:20-16:35 | Design of an 8-Channel 12Bits 1MSPS SAR ADC |
| Zhengxue Shi, Zhejiang University | |
| 16:35-16:50 | A 2A 4MHz Dual-Phase ZDS Hysteretic DC-DC Buck Converter with Peak Efficiency above 90% |
| Yanye Chen, Zhejiang University | |
| Poster Session: | |
| Correlation analysis between defect scanning and machine components | |
| Ming Guo, Shanghai Huali Integrated Circuit Manufacturing Co., Ltd | |
| Design and simulation of a PFM-PWM hybrid controller for DCDC converter with CLLC topology | |
| Hai Liu, Zhejiang University | |
| Improve SIP via Incomplete Cholesky Factorization | |
| Yang Yang, Fudan University | |
| High Efficient Automatic Power/Ground Layout Routing algorithm for Analog ICs | |
| Jiaxin Zuo, Fudan University | |
| Implementing Boolean Function by Ternary Content Addressable Memory with Approximate Match | |
| Jian Shi, Shanghai Jiao Tong University | |
| Verification of 100Gb/s Data-Rate Transceiving through Silicon-Photonic Module in an FPGA Platform | |
| C.-Z. CHEN, Peng Cheng Laboratory | |
| A 14.7mW 4Gbslane Wireless Through Silicon Interface for Memory Cube exploiting 16-QAM and Magnetic Resonance | |
| Chonghui Sun, Zhejiang University | |
| A Hardware Accelerator for Standard Convolution and Depthwise Convolution | |
| Fubang An, Fudan University | |
| A Multi-layer stacked 3-D SRAM system based on wireless transceiver using inductively coupled interface in 22-nm CMOS | |
| Kun Yang, Zhejiang University | |
| An Adaptive Controlled Chip-level Wireless Power Transfer System with DPID Controller for Wireless 3-D Stacked Chips | |
| Rushuo Tao, Zhejiang University | |
| An improved DNC sturdy 2-1 MASH Sigma-Delta modulator with Multi-bit SAR Quantizer | |
| Tengteng Mu, Xidian university | |
| A Front-end for 1.5GSPS 12bit Pipelined ADC | |
| Xiuheng Wu, Institute of Microelectronics, Chinese Academy of Sciences | |
| Security concerns over the cloud-oriented EDA solution | |
| Shiyue Qin, Northeastern University | |
| LUTPlace: An Improved Lookup Table-Based Placement for Routability | |
| Yihang Qiu, Guangdong University of Technology | |
| AcArm: A Novel Semiconductor Wafer Handling Robot | |
| Donglin Chen, Northeastern University | |
| Attention-based Mechanism for Technology Mapping Optimization | |
| Zhaohui Yang, Ningbo University | |
| An efficient ATPG technology based on Time Division Multiplexing method | |
| Lunmao Zhou, Sanechips Technology Co., Ltd | |
| A high-sensitivity and large-dynamic range readout circuit for polysilicon-based microbolometer | |
| Wei Zhu, Nanjing University | |
| Parallelizable Interval graph-based Branch-Cut algorithm for placement problems in VLSI | |
| Jiefu Yang, Northeastern University | |
| A Scalable And Configurable Low-Power Mixed Signal Neuromorphic Accelerators For Spiking Neural Network | |
| Yekuan Chen, Zhejiang University | |
| Convolutional Neural Networks on the Edge: A Comparison Between FPGA and GPU | |
| Xinfei Guo, Shanghai Jiao Tong University | |
| Logic optimization sequence tuning based on policy search deep reinforcement learning | |
| Haijiao Huang, Beijing University of Chemical Technology | |
| A 2-D Multi-dielectric Capacitance Solver Based on Floating Random Walk Method | |
| Jiahao Xu, Tsinghua University | |