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Masanori Hashimoto received the B.E., M.E., and Ph.D. degrees in communications and computer engineering from Kyoto University, Kyoto, Japan, in 1997, 1999, and 2001, respectively. Now, he is a Professor with the Department of Information Systems Engineering, Osaka University, Osaka, Japan. His current research interests include computer-aided design for digital integrated circuits, design for manufacturability and reliability, timing and power integrity analysis, reconfigurable computing, soft error characterization and low-power circuit design.
Dr. Hashimoto was a recipient of the Best Paper Award at ASP-DAC 2004 and RADECS 2017, and of IEICE Transactions on Fundamentals in 2016. He was on the technical program committees of international conferences including DAC, ICCAD, ITC, Symposium on VLSI Circuits, ASP-DAC, DATE, and IRPS. He serves/served as editor-in-chief for Elsevier Microelectronics Reliability and an associate editor for IEEE Transactions on VLSI Systems and Circuits and Systems I, and ACM Transactions on Design Automation of Electronic Systems.
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