(** to designate keynote talk, * to designate invite talk)
Sunday, March 12, 2017 Shanghai International Convention Center
Meeting Room: 5th Floor Yangtze River Hall 长江厅
Session I: Integration -- FEOL
Session Chair: Zhen Guo
| **13:30-14:00 | More-Moore Versus More-than-Moore and a Future of 50 Billion Connected Devices |
| Aaron Voon-Yew Thean, IMEC Fellow, VP of logic, National Signgapore University | |
| **14:00-14:30 | Interconnect Reliability Challenges for the 7nm Node and Below |
| Tony Oates, TSMC / IEEE Fellow | |
| **14:30-15:00 | The Technology Trend of IC Manufacture During Post Moore's Era |
| Hanming Wu, SMIC | |
| **15:00-15:30 |
The challenge of Si Development in the nanoscale era |
|
Charles
Chu, LAM Fellow |
|
| 15:30-15:45 | Coffee Break |
Session II: Thin Film -- FIN FET
Session Chair: Xiaoping Shi
| **15:45-16:10 | HK-metal Gate Engineering with Good Control of Dipole at HK-metal Gate Interface in sub-20nm FinFET Technology |
|
Lijie Zhang, SMIC |
|
| 16:10-16:25 |
FIN CRITICAL DIMENSION LOADING CONTROL BY DIFFERENT FIN CUT APPROACH FOR FINFETS PROCESS |
|
Qingpeng Wang, SMIC |
|
| 16:25-16:40 |
Fin bending mechanism investigation for 14nm FinFET technology |
|
Cheng Li, SMIC |
|
| 16:40-16:55 |
OXIDE FOOTING REDUCTION IN STI RECESS PROCESS FOR FINFETS BEYOND 20NM |
|
Qingpeng Wang, SMIC |
|
| 16:55-17:10 |
FINFETS WORK FUNCTION METAL GATE
INTEGRITY IMPROVEMENT THROUGH POST TREATMENT |
|
Lijuan Du, SMIC |
|
| Poster Session: | Location: Foyer of Yangtze River Hall |
| Coffee Break | Laser Spike Annealing And SiGe Dummy Pattern Layout Study Improve Contact Misalignment Overlay Issue |
| Ma Guiying, Semiconductor Manufacturing International Corporation | |
| Investigation of intrinsic hydrogenated amorphous silicon (a-Si:H) thin films on textured silicon substrate with high quality passivation | |
| Min-Lun Yu, National Central University | |
| SiCxN stack film as Cu capping layer in Cu/ULK interconnect for 28LP | |
| Yi Hailan, Shanghai Huali Microelectronics Corporation | |
| The Methodology to Reduce Poly Bump Defect | |
| Junlong Kang, Shanghai Huali Microelectronics Corporation | |
| Pre-treatment for e-SiGe Epitaxy growth in 16nm FinFET Process Engineering | |
| Renxu Yu, Semiconductor Manufacturing International Corporation (SMIC) | |
Monday, March 13, 2017 Shanghai International Convention Center
Meeting Room: 5th Floor Yangtze River Hall 长江厅
Session III: Thin Film -- HK MG
Session Chair: BeiChao Zhan
| *8:30-8:55 | Oxide based thin films for Current and Emerging Logic Applications |
| Vijay Narayanan, IBM | |
| *8:55-9:20 |
14nm metal gate film stack
development and challenges |
|
Jianhua Xu, SMIC |
|
| *9:20-9:45 | nS Anneal for Advanced CMOS Technologies |
| Liu Jinping, Globalfoundries | |
| *9:45-10:10 |
Review of thin film porosity characterization approaches |
|
Konstantin P. Mogilnikov, Leuven Instruments Co. Ltd |
|
| 10:10-10:25 | Coffee Break |
Session IV: Thin Film
Session Chair: Zhao Chao
| 10:25-10:40 |
Investigation of Effects of Atomic
Layer Deposition Process on MoS2 Channel Layer for Improved MoS2 FET
Characteristics |
|
Whang Je
Woo, Yonsei University |
|
| 10:40-10:55 | The application of the Smoluchowski effect to explain the current-voltage characteristics of high-k MIM capacitors |
| Wai Shing Lau, Zhejiang University | |
| 10:55-11:10 | The study of the impurity in HK film |
| Yingming Liu, Shanghai Huali Microelectronics Corporation | |
| 11:10-11:25 | The Deposition of High-k Dielectric Thin Films by Using ALD for Ge- and Graphene-based Devices |
| Il-Kwon Oh, Yonsei University | |
| 11:25-11:40 | Study of High-k treatment process in advance HKMG technology |
| Hailong Liu ,SMIC | |
| 11:40-11:55 | 14 NM FINFETS PMOS Source/Drain recess optimization |
| Youliang Jing ,SMIC | |
| 11:55-13:30 | Lunch Break |
Session V: Integration -- BEOL
Session Chair: Huang Liu
| **13:30-13:55 | New thin film material challenges for semiconductor memory industry |
| Er-Xuan Ping, AMAT | |
| **13:55-14:20 | New Challenges and High Productivity Solutions for Tungsten Metallization in Memory and Logic |
| Frank Huang, Lam Research | |
| *14:20-14:45 | Development of PVD technology for next wave IC packaging interconnection |
| Peijun Ding, NAURA, China | |
| 14:45-15:00 | The Study of 28nm BEOL Cu Gap-fill Process |
| Yu Bao, Shanghai Huali Microelectronics Corporation | |
| 15:00-15:15 | Nickel Silicide Anneal Process Research for 28nm CMOS Node |
| Zhenping Wen, Shanghai Huali Microelectronics Corporation | |
| 15:15-15:30 | Advanced Analytical Methods for Studying Ni Plating Baths used for Filling Through Silicon Vias |
| Mark Joseph Willey, MLI | |
| 15:30-15:45 | Coffee Break |
Session VI: New technology
Session chair: Jason Tian
| 15:45-16:00 | Rotary Spatial Plasma Enhanced Atomic Layer Deposition – an enabling manufacturing technology for μm-thick ALD films |
|
Sami Sneck, Beneq Thin Film Equipment |
|
| 16:00-16:15 |
Evaluation of new poly CVD tool in advanced MOSFET Technology |
|
Haifeng Zhu, SMIC |
|
| 16:15-16:30 |
Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film |
|
Ching-Lin Tseng, National central university |
|
| 16:30-16:45 |
A Noval ALD Low-k SiN film for Parasitic Capacitance Reduction in FinFETs technology |
|
Xue Xia, SMIC |
|
| 16:45-17:00 |
Method of Forming a More Robust Sidewall Spacer with Lower k (Dielectric Constant) Value |
|
Tao Han, Global Foundry |
|